Cache sizes, fabric latencies, clock speeds, I/O chip performance, DDR4 speeds and other aspects have not been disclosed, so there is still a long way to go until we have a full picture. But from own experience with Threadripper and current Epyc chips I can only STRONGLY STRONGLY discourage anyone from getting onto the AMD fan wagon when trying to solve GPU compute and HPC problems.As a reminder, here is the Intel Xeon Scalable “Cascade Lake-SP” overview:I realized this would be a terrible hypothetical waste of capabilities, but the architecture that I most desire, which has only leapt into my mind upon comprehension of the most immediate details, is:The bigger question is whether this will matter. Traditional enterprise may well be a lumbering beast and more amenable to kickbacks from Intel, I doubt the same can be said of 7+1Generalized bus routes, direct and switching, to cope with Optane DIMMs and everything under the sun.
I am wondering, if Optane expansion cards, on switched busses, when used to buffer DIMMs , will suffer greatly, in my application case, where the buffer is feeding fresh data for indexing, that’s random. This is as significant as the Carnegie Mellon prediction of”3M” workstations; megapixel, megabyte RAM, megahertz processing, which I have etched in my mind, growing up anticipation of the day of that breakthrough. For now, here is a tally of where we are:I am afraid that the idea of a sixteen core, top clock and max cache chip with PCIEv4, totally threw me, earlier. CPU Type: Dual AMD EPYC 7000-series; DDR4 Standard: DDR4 2666 MHz Registered ECC, 288-pin gold-plated DIMMs; Maximum Memory Supported: Supports up to 2TB Registered ECC DDR4 2666 MHz SDRAM in 16 x DIMMs; PCI Express 3.0 x16: 2; Model #: MBD-H11DSIN702MA015O; Item #: …
Doing interconnects is not a low-power affair. Do you have any insider info/leak for this? But I will be pursuing my interest in how Optane Squared, is handled by different architecture. STH to me, is only superficially about servers. We are using a third party service to manage subscriptions so you can unsubscribe at any time.Fabric for a”tray” or horizontal card for MXM GPU units.I really would like to see AMD lower the latency of their design, once they achieve that then they will truly have an architecture that can replace Xeon:s in all workloads“Rome will be a monster design, but the enterprise market is slow to move” While perhaps true, nearly half the market these days is ‘cloud’ who are not slow to move.
Rome will be a monster design, but the enterprise market is slow to move.This has just caused me to cry out Bingo! Having had a chat here, I will say generally the reason is that we can then ship workstation type boxes, capable of delivering our business stack on the user’s desk. AMD reported record revenue of $1.93 billion (up 26% YoY), along with record notebook and EPYC CPU sales in its 2Q 2020 earnings report today. Beyond that, AMD still needs to sell chips. All of the system vendors that we talk to know that Rome is going to be big. These new processors are the parts of ROME family and currently being sampled to consumers.
i guess it will increase latency a bit ..but will be more consistent.
the company is “betting big on 7nm” and the innovations that come with it. Until we learn more, we are not going to assume this is a mainstream product.Gen1 v. Gen2 EPYC is not just about the 7nm x86 chiplets. ?Here is the quick summary of what we learned today about the AMD EPYC 2 “Rome” generation:David, I am going to give you another thought on this one. But we have, from one view, the great niche market storage converged infrastructure application, if only the storage world didn’t pass over the big cache, high clock and low core count SKUs the kind that we are inseparable from.I had a drink with Scott last evening along with Ian Cutress, Paul Alcorn, and Charlie Demerjian.This is a long list. The entire discussion about PLX, Skylake-SP mesh, …., has become completely irrelevant for the GPU compute crowd. Although i am more interested to find out how it will impact the frequency of those chiplets..actual cores… since IO is out into another chip….cores might be able to Turbo better..or even have higher base frequency.“Ability to connect GPUs and do inter-GPU communication over the I/O chip and Infinity Fabric protocol so that one does not need PCIe switches or NVLink switches for chips on the same CPU.
AMD also notched a … I will want to test, soonest possible, naturally. SUPERMICRO MBD-H11DSI-NT Mainboard, Factory Installed with 2 x AMD EPYC Rome 64 Cores 7702 CPU.
CEO of AMD Lisa Su said. This was in prototype system as AMD yet has to optimize it further. PCIe Gen4 support providing twice th…